RF/Analog Mixed signal IC design opening in Shanghai

sansanlin

<PRE><B>Dear Friend</B>
<B></B>How are you?

We have some IC design JOB OPENING in CA(USA),Shanghai and Suzhou(China).
If you are interested in these jobs, please send your resume
with job title and preferred location to [email protected] or apply online.
If your friends are qualified, please kindly forward to them.
Please check <a href="http://www.jmep.com/" target="_blank" >http://www.JMEP.com</A> for details.  

Employer RF Design Company
Description
Company is a fabless RFIC design company focusing on Greater China's niche
but explosive market of wireless communications such as PHS, 2.4GHz ISM band
applications, and Chinese specific markets such as TD-SCDMA 3G mobile, Chinese GPS
systems and Digital and HD TV tuners, etc.

Job Id 1076 Job Title RFIC Design Engineer/Manager
Annual Salary Negotiable
Job Description
RFIC Design Engineer/Manager (2 persons)
Location: CA,US or Shanghai

Requirements:
1) MSEE or PhD, approximately 3-5 years industry experience.
2) Hands-on design experience with LNA, mixer, PLL, VCO, filter, etc with Cadence is required.
3) Knowledge about device modeling and RF system.
4) Good English communication skills.

   
Job Id 1075 Job Title Analog/Mixed-signal Design Mgr
Annual Salary Negotiable
City SHANGHAI
Job Description
Job Description:
Analog/mixed IC design Engineer/Manager
Requirements:
1) MSEE or PHD, approximately 3-5 years industry experience;
2) Hands-on design experience with PLL, filter, D/A, A/D and Sigma--delta, etc with Cadence is required.
3) Good knowledge about device modeling and RF system. Good English communication skills.

微电子设计 Micro-electronic Design Company Location: Suzhou
Senior IC Backend Design E. /Manager

Request:
●1. MSEE or above, and 3+ years ASIC backend design experience
●2. Good insight of entire backend design flow
●3. Experience with floor plan, place and route, clock tree synthesis, physical synthesis, signal integrity and layout verification tools
●4. Experience of hierarchical design flow
●5. Experience of hi-end project design (i.e. hi frequency or multiple clocks)
●6. Use of UNIX Utilities such as awk, perl, C and others

Senior Algorithm Implementation Engineer/Manager
要求
●1. 电子、电机等相关专业硕士以上 （博士优先）
●2. 精通C语言或MATLAB
●3. 精通图象及通信的算法与实现
●4. 懂电视信号、色彩转换及通信，并有类似开发和实现经验
●5. 有MPEG经验者优先

Request
●1. Must have MSEE or equivalent (Ph.D preferred)
●2. Must have extensive experience in C/C++ &amp; Matlab
●3. Must have in-depth experience with Video/Imagine &amp; Telecom technologies &amp; algorithms
●4. Must have excellent working knowledge of TV Codec, Color Space Transfer and processes with hands-on R&amp;D and implementation experience
●5. Experience with MPEG is a big plus

   
Design Verification Engineer
Responsibilities

●Participate in all phases of VLSI development from concept, architecture, to implementation.
●Work within a cross-functional team environment to complete evaluation of specific chip design.
●Develop and setup the verification environment and methodology for the advanced products SOC in consumer electronics
●Create test plans for both unit-level and chip-level environments
●Design and implement design verification environments
●Write tools in Perl and shell scripts
●A strong background in Verilog HDL and logic verification tools and methodologies is required, including simulation, test bench setup, formal verification, and code coverage
●Generate tests and debug the Verilog design

●Requirements:

●Must be strong in Verilog and Perl programming
●Must be good in communication skills
●Must be able to work well as a team.
●Minimum of 5 years experience in complex ASIC verification and/or ASIC design, with good track record of chip designs.
●BS in Electrical Engineering or Computer Engineering, MS preferred


Job AD expired Date: Jan 1, 2005
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Phone: 1 (650)365-4473 (10:00am - 10:00pm US West Coast Time) or eMail: [email protected]  
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